PPCL

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Memory Model Background Definitions

History

• Version with fences(=hwsync) and a modification to B-cumulativity assumed for the purposes of the SC proof: PPCL Formulation of Feb 18 2007
• Version of 03/07/07: Removes modification of B-cumulativity. Uses stronger formulation of Completion Assumption (consistent with its informal definition). Introduces lwsync as well as hwsync. Assumes all events are visible at all processors. (All these changes are consistent with the PPC architecture.)
• Version of 03/28/07: Removed mistaken assumption that all stores are performed wrt all processors.

PPCL

Formulation of 03/07/07.

Revised 03/28/07.

Commentary on PPCL Model

Not yet updated for 03/28/07 version: PPCL is Sequentially Consistent

In this model we make the Completion Assumption:

When a load l being executed by a processor p=p(l) completes, it has been performed with respect to all processors.

This assumption introduces a partial order, <, on loads. Introduce the function time(e,p) to specify the time (a number) at which the event e is performed at processor p. We require that global time is consistent with the processor's view of time: that is, d <p e implies time(d,p) < time(d, e). Now the Completion Assumption can be formalized by: for any load k, for all processors p other than p(k), time(k,p) < time(k, p(k)). Now we can define k < l (for loads k and l) by: time(k,p(k)) < time(l, p(l)). The following axioms are now true:

k <k l implies k < l

k < l < m implies k < m

k < l implies k <l l

Below we shall take these three axioms as given, and not introduce time(k,p) explicitly.

The model has the following elements:

E -- set of load and store events

< -- a total order over S(a), for all a in A

<p -- a partial order over E that is total on E(p) u L, for each p in P.

It will be useful in what follows to think of events e as being local to the processor p(e), and remote or foreign to processors different from p(e).

Further we define for every processor p in P: V(p) = {d | for some e in E: d <p e or e <p d}

The tuple (E, <1,..., <n, <) is a valid execution if the conditions (C), (V), (HW1), (HW2), (LW1), (LW2), (C), (T) and (T1) are satisfied.

Coherence: The order in which writes are visible at any processor is consistent with the global order <. Formally:

(C) for any processor p, for any address a in A, stores s,s' in S(a) s <p s' implies s < s'.

Value flow: Let us define for every store s in S(a), loads(s), the set of loads which read from s by:

loads(s) = { l in L(a(s)) | s <p(l) l, forall s' in S(a(l)): s' <p(l) l implies s' <p(l) s or s'=s }

Each load gets the value of the latest preceding store to the same address that the processor observes, or the initial value if there is no such store. Formally, we require for all processors p:

(V) for all loads l in L(p): v(l) = i(a(l)) or for some s in S(a(l)): s <p(l) l

Fences: There are two kinds of fences, hwsync, and lwsync. Fences order memory accesses. For an hwsync hw and processor p=p(hw) both the following conditions must hold:

(HW1) for all d in E, e in E(p): d <p hw <p e implies for all q in P: e in V(q) implies d <q e

(HW2) for all d in E, s in S(p), l in loads(s), e in E(l): d <p hw <p s, l <l e implies for all q in P: e in V(q) implies d <q e

For an lwsync lw and processor p=p(lw) both the following conditions must hold. These conditions are the same as for hw, except that they do not apply to (store, load) pairs:

(LW1) for all d in E, e in E(p): d <p lw <p e, not(d in S, e in L) for all q in P: e in V(q) implies d <q e

(LW2) for all d in E, s in S(p), l in loads(s), e in E(l): d <p lw <p s, l <e e, not(d in S, e in L) for all q in P: e in V(q) implies d <q e

Completeness Assumption:

(C) for all loads k, l: k <k l implies k < l

(T) for all loads k,l,m: k < l, l < m implies k < m

(T1) for all loads k, l: k < l implies k <l l

(L1) for all loads k, stores s in S(a(k)): not (k <p(s) s and s <p(k) k) and not (s <p(s) k and k <p(k) s)