Excerpts from the PowerPC Architecture Redbooks

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of Contents

These extracts are taken from [1].

Contents 1 Peformed wrt processor p 2 Memory Coherence Required 3 Barrier 4 Sync

Peformed wrt processor p

From [PPC-2,p10], the definition of performed w.r.t a processor p:

A load or instruction fetch by a processor or mechanism (P1) is performed with respect to any processor or mechanism (P2) when the value to be returned by the load or instruction fetch can no longer be changed by a store by P2. A store by P1 is performed with respect to P2 when a load by P2 from the location accessed by the store will return the value stored (or a value stored subsequently).

Memory Coherence Required

From [PPC-2, p5, Sec 1.6.3]:

An access to a Memory Coherence Required storage location is performed coherently, as follows.

Memory coherence refers to the ordering of stores to a single location. Atomic stores to a given location are ''coherent'' if they are serialized in some order, and no processor or mechanism is able to observe any subset of those stores as occurring in a conflicting order. This serialization order is an abstract sequence of values; the physical storage location need not assume each of the values written to it. For example, a processor may update a :location several times before the value is written to physical storage. The result of a store operation is not available to every processor or mechanism at the same instant, and it may be that a processor or mechanism observes only some of the values that are written to a location. However, when a location is accessed atomically and coherently by all processor and mechanisms, the sequence of values loaded from the location by any processor or mechanism during any interval of time forms a subsequence of the sequence of values that the location logically held during that interval. That is, a processor or mechanism can never load a ''newer'' value first, and then, later, load an ''older'' value.

Barrier

From [PPC-2,p15,Sec 1.7.1]:

When a processor (P1) executes a Synchronize or eieio instruction a memory barrier is created, which orders applicable storage accesses pairwise, as follows. Let A be a set of storage accesses that includes all storage accesses associated with instructions preceding the barrier-creating instruction, and let B be a set of storage accesses that includes all storage accesses associated with instructions following the barrier-creating instruction. For each applicable pair a_i, b_j of storage accesses such that a_i is in A and b_j is in B, the memory barrier ensures that a_i will be performed with respect to any processor or mechanism, to the extent required by the associated Memory Coherence Required attributes, before b_j is performed with respect to that processor mechanism.

The ordering done by a memory barrier is said to be cumulative if it also orders storage accesses that are performed by processors and mechanisms other than P1, as follows:

• A includes all applicable storage acccesses by any such processor or mechanism that have been performed with respect to P1 before the memory barrier is created.

• B includes all applicable storage accesses by any such processor or mechanism that are performed after a Load instruction executed by that processor or mechanism has returned the value stored by a store that is in B.

Sync

From [PPC-2,p.~26,Sec 3.3.3]:

The sync instruction creates a memory barrier (see Section 1.7.1). The set of storage accesses that is ordered by the memory barrier depends on the value of the L field.

• L=0 (heavyweight sync) The memory barrier provides an ordering function for the storage accesses associated with all instructions that are executed by the processor executing the sync instruction. The applicable pairs are all pairs a_i,b_j in which b_j is a data access, except that if a_i is the storage access caused by an icbi instruction then b_j may be performed with respect to the processor executing the sync instruction before a_i is performed with respect to that processor.
• L=1 (lightweight sync) The memory barrier provides an ordering function for the storage accesses caused by Load, Store, and dcbz instructions that are executed by the processor executing the sync instruction and for which the specified storage location is in storage that is Memory Coherence Required and is neither Write Through Required nor Caching Inhibited. The applicable pairs are all pairs a_i,b_j of such accesses except those in which a_i is an access caused by a Store or dcbz instruction and b_j is an access caused by a Load instruction.

The ordering done by the memory barriers is cumulative.

If L=0 (or L=2), the sync instruction has the following additional properties:

• Executing the sync instruction ensures that all instructions preceding the sync instruction have completed before the sync instruction completes, and that no subsequent instructions are initiated until after the sync instruction completes.

• The sync instruction is execution synchronizing (see Book III, PowerPC Operating Environment Architecture). However, address translation and reference and change recording (see Book III) associated with subsequent instructions may be performed before the 'sync instruction completes.

• The memory barrier provides the additional ordering function such that if a given instruction that is the result of a Store in set B is executed, all applicable storage accesses in set A have been perforemd with respect to the processor executing the instruction to the extend required by the associated memory coherence properties. The single exception is that any storage access in set A that is caused by an icbi instruction executed by the processor executing the sync instruction (P1) may not have been performed with respect to P1 (see the description of the icbi instruction onpage 18).

The cumulative properties of the barrier apply to the execution of the given instruction as they would to a Load that returned a value that was the result of a Store in set B.

The sync instruction provides an ordering function for the operation caused by dcbr instruction with TH_0=1.

The value L=3 is reserved.

The sync instruction may complete before storage accesses associated with instructions preceding the sync instruction have been performed. The sync instruction may complete before operations caused by dcbt instructions with TH_0 = 1 preceding the sync instruction have been performed.